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[VHDL-FPGA-Verilog] XC4VLX60MB_Lab3_RS232_ISE91

Description: FPGA design, In addition to logic design, the future also can be SOC (System On Chip) approach to achieve a future A complete design system, so XC4VLX60 the board design includes RS232 and LCD surrounding the design, this experiment will Super terminal RS232 and PC connectivity for asynchronous data transmission, as RS232 verification and practice.-FPGA design, In addition to logic design, the future also can be SOC (System On Chip) approach to achieve a future A complete design system, so XC4VLX60 the board design includes RS232 and LCD surrounding the design, this experiment will Super terminal RS232 and PC connectivity for asynchronous data transmission, as RS232 verification and practice.
Platform: | Size: 498688 | Author: vkiy | Hits:

[USB develop] CIS

Description: 程序主要实现EZ-USB的控制功能，加上BORD-CONTROL两个程序实现FPGA控制CIS图像采集程序的数据保存，并传输到PC机上进行数据保存-Program mainly realizes the ez-usb CONTROL functions, plus BORD CONTROL- two program CONTROL of CIS image acquisition program FPGA, and the data transmission to PCS data storage
Platform: | Size: 2036736 | Author: 袁官福 | Hits:

[VHDL-FPGA-Verilog] rs232

Description: 本设计是PC和FPGA的串口通信的程序，用的是VERILOG语言，调试成功，用户可根据自己的项目稍作改动。-The design is a PC and the FPGA' s serial communication procedures, using a VERILOG language, debugged, the user can make a little change according to their own projects.
Platform: | Size: 2048 | Author: 陆景鹏 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 利用串口调试助手是实现pc机和fpga的串口通信功能，程序附注释。-Debug Assistant is achieved using serial pc machine and fpga serial communication function, the program annotated.
Platform: | Size: 102400 | Author: 郝强 | Hits:

[VHDL-FPGA-Verilog] PS_port

Description: PS协议用FPGA实现，模拟键盘与PC通信-PS agreement with the FPGA, analog keyboards and PC communication
Platform: | Size: 229376 | Author: lining | Hits:

[VHDL-FPGA-Verilog] FT2232H_USB_Core

Description: 在FPGA外扩用FT2232 实现UART TO USB 2.0 的通信。-The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style synchronous FIFO mode. Data rates up to 25 mbytes/s can be achieved. The core has internal FIFOs on the receive and transmit for improved throughput. For more information see FTDI s appnote "AN_130_FT2232H_Used_In_FT245 Synchronous FIFO Mode.pdf" Included: VHDL core, NIOS test application, PC test application
Platform: | Size: 6144 | Author: 李涛 | Hits:

[VHDL-FPGA-Verilog] sim_uart

Description: uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； -verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through
Platform: | Size: 2048 | Author: 周西东 | Hits:

[VHDL-FPGA-Verilog] rec

Description: 基于vhdl编写的FPGA与PC串行通信的接收信号解码程序，调试已通过。-Vhdl prepared based on FPGA and PC serial communication received signal decoding process, debugging has been passed.
Platform: | Size: 1024 | Author: 郭暧闵 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 利用FPGA接受232芯片的串口数据，可以与PC进行串口通信-FPGA chip using the serial data received 232, serial communication with PC
Platform: | Size: 1189888 | Author: 杨然 | Hits:

[VHDL-FPGA-Verilog] digoscill

Description: 完成FPGA采集功能以及控制上位机的程序-Complete the acquisition FPGA features and procedures for the control PC
Platform: | Size: 4091904 | Author: 李振强 | Hits:

[VHDL-FPGA-Verilog] T13_USB

Description: 本示例为基于FPGA红色飓风一代IDS-EP1C6/12开发板的USB传输，实现了pc端接收来自FPGA开发板的数据，并显示条纹，具体使用说明见解压后的说明文档。-This example is based on red hurricane generation FPGA development board' s USB transfer IDS-EP1C6/12 realized pc client receives the data from the FPGA development board and display stripes, detailed instructions, see the documentation after decompression.
Platform: | Size: 6283264 | Author: jiang | Hits:

[VHDL-FPGA-Verilog] fpgaPfirmwarePpc

Description: 用FPGA做USB2.0通信的实验，完成SLAVE FIFO模式下的数据传输，里面包括固件程序，还有上位机（Ｃ＋＋）程序。-USB2.0 communication with the FPGA to do the experiment, complete the SLAVE FIFO mode data transmission, which includes firmware, and PC (C++) program.
Platform: | Size: 3322880 | Author: 王金凤 | Hits:

[File Format] Seria_M

Description: in this part of source code i added the code for interface the rs-232 with pc and connected it to the fpga spartan-3e in order to transmit data and receive it -in this part of source code i added the code for interface the rs-232 with pc and connected it to the fpga spartan-3e in order to transmit data and receive it
Platform: | Size: 243712 | Author: Mohammed | Hits:

[VHDL-FPGA-Verilog] LogicAnalyzer

Description: 用java做的逻辑分析上位机软件，下位机用xilinx的fpga实现-Logical analysis of java to do with PC software, the next crew to use xilinx fpga implementation of
Platform: | Size: 18313216 | Author: 何志峰 | Hits:

[VHDL-FPGA-Verilog] serial

Description: 程序实现fpga与pc机的通讯，verilog语言-Program realization fpga with the PC communications, verilog language
Platform: | Size: 3072 | Author: 白羽 | Hits:

[VHDL-FPGA-Verilog] EDK_lab_chinese

Description: Almighty-EDK开发套件是一款以Xilinx最新90ns工艺的Spartan3S700A FPGA为核心，以 USB2.0及RJ45，VGA，AC97接口应用为主要针对市场的产品，利用Almighty开发板上的高效低成 本ADC及FPGA外围大容量SDR SDRAM、Nor Flash存储器，配合使用FPGA内部的乘法器单元、 逻辑单元及MicroBlaze软核处理器，用户可以搭建强大的SOC应用平台，同时Almighty开发套件支 持通过USB2.0/RS232等PC接口与计算机相连进行高速数据交互，无论是进行课题研究还是进行产 品设计，无论是FPGA设计还是ASIC原型验证，Almighty功能及性能上都表现卓越。依元素科技为 该项产品提供丰富的例程及培训支持，利用Almighty套件进行项目设计将是您的最佳选择-sdfhsdfhsdfhsfhserywfghsrey sh
Platform: | Size: 1842176 | Author: 林 | Hits:

[VHDL-FPGA-Verilog] A-Simplified-VHDL-UART

Description: In embedded systems, the processor that we choose for our design may not come with built-in peripherals. Therefore, designers will have to implement these devices in hardware keeping in mind that they will need to interface to the processor. In this lab we will design a simplified UART (Universal Asynchronous Reciever Transmitter) in VHDL and download it to the FPGA on the XS40 baord. Serial communication is often used either to control or to receive data from an embedded microprocessor. Serial communication is a form of I/O in which the bits of a byte begin transferred appear one after the other in a timed sequence on a single wire. Serial communication has become the standard for intercomputer communication. In this lab, we ll try to build a serial link between 8051 and PC using RS232.
Platform: | Size: 374784 | Author: mezzich | Hits:

[VHDL-FPGA-Verilog] task2

Description: Verilog语言，可在QuartusII正确运行，实现远程控制系统，利用异步串行通信，PC发送数据FPGA接收，实现本地回环模式。-清华大学电子课程设计：Verilog language, you can QuartusII correctly, remote control systems, using asynchronous serial communication, PC to send data received FPGA to achieve the local loopback mode.
Platform: | Size: 572416 | Author: 薛芬 | Hits:

[VHDL-FPGA-Verilog] task22constant

Description: 清华大学电子课程设计：Verilog语言，Quartus可以正确运行，下载到FPGA上可完成PC与FPGA一串数据的连续收发，且实现本地回环，异步串口通信-Verilog language, Quartus can be correctly downloaded to the FPGA to be completed by PC and FPGA transceivers continuous string of data, and implement local loop, asynchronous serial communication
Platform: | Size: 580608 | Author: 薛芬 | Hits:

[VHDL-FPGA-Verilog] system

Description: 清华大学电子课程设计：Verilog，QuartusII可正确运行，可下载到FPGA上，完成远程通信的整体任务，PC发数据，键盘输入运算符与运算数计算将结果显示在数码管上并返回给PC机，需异步串口调试软件-Verilog, QuartusII run correctly, can be downloaded to the FPGA, to complete the overall task of remote communication, PC send data, keyboard operators and operands calculation displays the results in digital tube and returned to the PC, to be asynchronous serial debugging software
Platform: | Size: 902144 | Author: 薛芬 | Hits:
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